The high speed performance characteristics of a field effect transistor (FET) depend on, among other things, the carrier mobility, the channel length, and the parasitic channel resistance of the device. Since the bulk mobility is substantially higher in GaAs than it is in silicon, substantially higher performance can be achieved using integrated circuits fabricated with GaAs than can be achieved with silicon for an equivalent speed-power product operation.
The early GaAs MESFET structures had relatively large gate to drain separation and gate to source separation. An article by Mead, entitled "Schottky Barrier Gate Field Effect Transistor", Proceeding of the IEEE 54, 307 (1966) describes such an early structure. These early MESFET structures typically had gate to source and gate to drain separation dimensions of the same order as the gate length. As a result, the minimum source to drain separation for such early structures was about three times the minimum gate length. Since only the region beneath the gate was electrically controlled for the conduction of electric current, the remaining two-thirds of the channel contributed to parasitic resistance as well as to an accompanying parasitic channel capacitance. Such early structures had a disadvantage of low level of circuit integration because of the rather large device size. The inherent parasitic effects of such early device structure also detrimentally impact its performance and pose a performance limit well below the fundamental performance limit of the GaAs MESFET.
Drangied in U.S. Pat. No. 3,609,477 addresses the problem of parasitic channel resistance. According to this patent, highly conductive materials are used in the parasitic channel region to thereby reduce the problem of parasitic channel resistance.
The problems of parasitic channel resistance are also appreciated in U.S. Pat. Nos. 3,855,690 and 3,943,622 to Kim et al. According to these patents, the parasitic channel resistance can be reduced by growing faceted source and drain regions, also known as mesas. These regions or mesas are spaced apart and with facets having overgrown edge portions. The faceted sources and drains are employed as masks for deposition of a gate. The overgrowth portion provides shielding of the surface in the immediate vicinity of the source and the drain, thereby preventing shorting between the source (or the drain) and the gate.
A prior self-aligned GaAs field effect transistor (FET) is described by Schwartz in U.S. Pat. No. 3,713,912. The disclosed structure includes an n type GaAs substrate and a semi-insulating layer bearing a conducting surface coating thereon. An insulated gate FEt is formed by generating a pair of windows in such layer and introducing either p type or n type material through the windows.
Another prior self-aligned GaAs FET structure is described in U.S. Pat. No. 4,111,725 to Cho et al. The disclosed device structure includes an n GaAs mesa serving as the gate bounded laterally by n+ GaAs epitaxial layers serving as source and drain. The source and drain layers are formed by molecular beam epitaxy and the resulting device is also an insulated gate FET (a MISFET), not a MESFET.
Triebwasser in U.S. Pat. No. 4,222,164 describes a self-aligned MESFET structure, wherein the channel spacing between the drain and source is substantially reduced. According to the patent, the source, drain and gate isolation is provided by an insulator therebetween. The disclosed device is fabricated on a semiconductor body having an epitaxial layer of opposite polarity thereon.